Project Details
Comprehensive documentation of the NBA⁺ SRAM implementation
Inverter
DRC & LVS Pass
Inverter Schematic
Area:0.3375 μm²
Sizing:0.45 × 0.75 μm²
Components:PMOS & NMOS
SRAM Cell
DRC & LVS Pass
SRAM Cell Layout
Area:1.224 μm²
Dimensions:1.632 × 0.75 μm²
NAND Gate
DRC & LVS Pass
NAND Gate Layout
Area:0.5595 μm²
Dimensions:0.746 × 0.75 μm²
SNM:165 mV
Row Address Decoder
DRC & LVS Pass
Decoder Layout
Area:24.714 μm²
Dimensions:13.73 × 1.8 μm²
Function:Row access
Write Driver
Implemented
Write Driver Circuit
Components:Inverters, NAND
Signals:R/W, Din, CLK
Outputs:BL, BLB
Sense Amplifier
Implemented
Sense Amplifier Circuit
Inputs:BL, BLB, SE
Function:Signal detection