SRAM Interactive Demo
NBA⁺ SRAM Array Simulator
SRAM Array (4×4)
16 bits (2 Bytes)
Select a cell to begin
Signal Waveform
Waveform Description:
- Wordline (WL): Activates at 10ns, connecting the cell to bitlines
- Bitline (BL): Precharged high, remains high when reading a '1'
- Bitline Bar (BLB): Precharged high, discharges slightly when reading a '1'
- Cell Node (Q): Remains stable at 1 during read
- Cell Node Bar (QB): Remains stable at 0 during read
- Sense Amp (SA): Activates at 25ns, detects and amplifies the bitline differential
Pattern Generator
Operation Log
Memory Output
0 bits set
00000000
Real-Time Metrics
0/16 bits
Idle
SRAM Architecture
Developed by Aaron - Hardware/Software Integration
Row Decoder
Sense Amplifiers
Write Drivers
I/O Circuit
Row Decoder
Write Drivers
Sense Amplifiers
I/O Circuit