NBA⁺ SRAM Project
A comprehensive VLSI design implementation for ENGR 848 at San Francisco State University
Nick, Bisum, Aaron
Summary of Results
Key achievements and metrics from our SRAM implementation
Inverter
DRC & LVS Passing
Area = 0.45 × 0.75 = 0.3375 μm²
PMOS and NMOS transistors
SRAM Cell
DRC & LVS Passing
Area = 1.632 × 0.75 = 1.224 μm²
NAND Gate
DRC & LVS Passing
Area = 0.746 × 0.75 = 0.5595 μm²
SNM = 165 mV
Interactive Demo
Full-stack implementation
Hardware-software integration
Real-time visualization
VLSI Design
SRAM Array Implementation
Our project implements a complete SRAM array with all necessary components for read and write operations.
- 8×16 SRAM Array (128 bits / 16 Bytes)
- Area = 13.793 × 12.92 = 178.21 μm²
- Passed DRC & LVS checks
- Complete read/write functionality
SRAM Array Visualization
SRAM Array Functionality
Understanding how our SRAM implementation works
8×16 SRAM Array
- Stores data in a matrix of rows and columns
- Each row is accessed by a row address decoder
- Data is written or read one row at a time
- 128 bits (16 Bytes) total storage
- Area = 13.793 × 12.92 = 178.21 μm²
Interactive Demo Features
- Real-time bit manipulation and visualization
- Simulated read/write operations with animations
- Multiple pattern generation options
- Developed by Aaron with hardware-software integration